: Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.
: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Knowledge of EM/IR requirements. Compiler level integration, verification of Compiler/Custom memories. Should possess good knowledge on CMOS fabrication process, foundries and challenges in latest technology nodes. Memory Compiler Architecture.
: Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills.
Qualifications
Layout Design, Analog Design, and IC Layout skills
Proficiency in Cadence tools and Page Layout
Experience in creating memory layouts
Bachelor's or Master's degree in Electrical Engineering or related field
