Memory Design Verification Engineer

Job Title: Memory Design Verification Engineer

Location: Electronic city, Bangalore (work from office)

Duration: Full time (Permanent)

We are looking for energetic and passionate memory design verification engineers for the development of memory compilers and custom macros of all types on the leading edge of process technology. Typically requires a minimum of 6+ years of relevant experience.

Job Description Summary

Contribute towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 3nm and other cutting edge process technologies

Job Description

Contribute towards Memory Design Validation of all types of custom memory macros and memory compilers

Perform functional verification, root cause design discrepancies, and help resolve them

Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them

Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them

Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins

Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them

Perform various QA and validation checks to ensure accurate timing and power models

Develop scripts to automate verification flow and data analysis

Support silicon debugs and correlation to spice models

Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan

Skill Sets

Strong expertise in development of memory macros of all types and architectures

Strong understanding of transistor level circuit behavior and analysis

Good understanding of the layout and their related challenges in sub nanometer process technologies

Good understanding of signal integrity, EM/IR, and reliability analysis

Good understanding of memory behavioral and physical models

Good understanding of DFT Schemes and chip level integration

Proficient in running transistor level simulators, writing automation scripts, and are tools savvy

Complete hands on experience in using Cadence schematic/layout editor tools

Complete hands on experience with transistor level simulators, Monte Carlo variation analysis, waveform viewer tools such as; HSPICE, HSIM, XA, FineSim, XARA, nWave, waveform viewer, etc..

Experience in Skill/Perl/Python Scripting is a strong plus

Good communication, interpersonal, and leadership skills

Good debugging skills, problem solving and logical reasoning skills

Motivated, self-driven and good at multi-tasking