Description
We are seeking a Formal Verification Engineer to join our team. The ideal candidate will have 5-15 years of experience in formal verification with a strong background in digital design and verification methodologies.
Responsibilities
- Develop and implement formal verification methodologies to ensure the correctness of digital designs.
- Work closely with the design and verification teams to identify and resolve issues.
- Develop and maintain formal verification testbenches and test suites.
- Analyze and debug formal verification failures.
- Contribute to the improvement of formal verification methodologies and tools.
- Provide technical guidance to junior members of the team.
Skills and Qualifications
- Bachelor's or Master's degree in Electrical/Electronic Engineering or Computer Science.
- 5-15 years of experience in formal verification with a strong background in digital design and verification methodologies.
- Experience with formal verification tools such as JasperGold, Questa Formal, or FormalPro.
- Experience with industry standard verification languages such as SystemVerilog and e.
- Expertise in digital design and verification concepts.
- Strong analytical and problem-solving skills.
- Excellent communication and interpersonal skills.
- Ability to work independently and as part of a team.
