We are seeking an experienced Sr. Staff Design Engineer for SoC. Responsible for leading and owning RTL development of one or more modules of a high-performance SoC and integration of the SoC. The candidate will be responsible for all aspects of the design including Integration, Performance, Power, and Area.
You will:
- Drive the micro-architecture and design multiple blocks of the SoC Ips or other control IPs.
- Perform Microarchitecture development and specification- from early high-level architectural exploration, through microarchitectural research and arrive at detailed specifications.
- Configure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals.
- Perform Functional verification support and assist in the design verification strategy
- Assist with the verification of RTL design performance goals
- Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power
Ideally, you'll have:
- Hands-on knowledge of high-performance microcontroller or Micro-processor architectures.
- Experience with simulators and waveform debugging tools.
- Knowledge of logic design principles along with timing and power implications.
- Knowledge of System Verilog, UVM, UPF and parametrized designs and configurable designs.
- Experience with major EDA tool vendor tools like Synopsys/Cadence/Tessent is desirable. Hands on knowledge of Synopsys Tools is preferable.
- In depth and hands on knowledge of bus architecture like AXI/AHB/equivalent protocols and various peripherals/CPU core integration.
- Excellent analytical and problem-solving skills.
- Masters or Bachelor's with 1-5 years of experience
A plus if you have:
- Experience with designing RISC-V, ARM, and/or MIPS CPU
- Understanding of low-power architecture techniques.
- Experience using a scripting language such as Perl or Python.
