Opportunity for a talented individual for their memory interface products.
We are looking for a candidate with a strong background in verifying complex integrated circuits.
- The candidate needs to have skills that are up to date with the latest IC verification tools and flow.
- The candidate will work closely with design, applications, and test engineering.
- In addition, strong collaboration and communication skills are a must.
Duties/Responsibilities:
- Develop verification testbench components for chip/module level using SystemVerilog, C, and Perl.
- Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment.
- Define and execute detailed verification plan from spec working with architects, designers, and system engineers.
- Incorporate code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness before tape-out.
- Debug tests, and run gate-level simulations.
- Develop automated/scripted design flows for the above-mentioned development processes.
- Participate in silicon debugging and analysis.
- Support generation of production test vectors.
Qualifications
- MS in Computer or Electrical Engineering with a minimum of 2+ years of experience in design/verification management of highly complex projects.
- Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
- Must be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (OVM, UVM).
- Must be proficient in Verilog (System Verilog preferred).
- Understanding or prior experience with Industry standard protocols like DDR4/DDR5 is preferred.
