DFT Engineer / Sr Engineer

Qualcomm Technologies, Inc

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Posted 6 months ago
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1-2 Years

Chennai, India

Job Description

Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques.

Primary responsibilities will include ,

Interfac e with design team to ensure DFT design rules and coverages are met.

Generating high quality manufacturing ATPG test patterns for stuck-at (SAF) , transition fault (TDF ) models through the use of on-chip test compression techniques.

M BIST verification (including repair), test pattern generation through Mentor tool.

ATPG (SAF, TDF) and MBI ST verification using unit delay and min/max timing corner s imulations .

Work with the P roduct /Test engineering teams on the delivery of manufacturi ng test patterns for ATE .

Responsible for supporting post silicon debug effort, issue resolution .

Responsible for Diagnostic Tool generation for ATPG , MBIST and bring-up on ATE.

Developing, enhancing and maintaining scripts as necessary

Minimum Qualifications:

Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.