2 to 4 years of experience in Verification with B.E/B.Tech/M.E/M.Tech.
Good knowledge on Verilog/System Verilog/UVM/OVM.
Knowledge of at least one scripting language like Python, Perl, Shell, TCL
Knowledge of at least one industry standard protocols like Ethernet, PCIe, USB, SATA, NVMe, AMBA, ARM, RISC CPUs etc.,
Able to work on functional coverage modelling and Code coverage analysis.
Experience in GLS will be added advantage.
Should have good documentation/communication skills and be able to work with multi-functional, multi-site teams
5 to 7 years of experience in Verification with B.E/B.Tech/M.E/M.Tech.
Good knowledge on Verilog/SystemVerilog/UVM/OVM.
Knowledge of at least one scripting language like Python, Perl, Shell, TCL
Knowledge of at least one industry standard protocols like Ethernet, PCIe, USB, SATA, NVMe, AMBA, ARM, RISC CPUs etc.,
Good RTL debugging skills.
Expertise in independently creating detailed test plan with well-defined functional coverage goals.
Hands on experience on GLS sims with SV UVM based env.
DV planning and risk mitigation
Communicate with all stakeholders (design, PD and HQ) for scheduled alignment, risk assessment and other responsibilities
Support post silicon team, DFT and PD team for characterization, vector generation and power analysis
