D o: Design Verification Engineer
: 5+ Years
: Bangalore/Bhubaneswar
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- Develop and execute verification plans for complex RTL designs.
- Perform functional and performance verification of design blocks.
- Collaborate with cross-functional teams to ensure successful IP component integration.
- Contribute to enhancing verification methodologies and best practices.
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Bachelor's or master's degree in electrical engineering/Electronics & Communication Engineering or related field.
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Minimum of 5+ years of experience in RTL design verification.
Proficiency in Verilog/ System Verilog and experience with industry-standard verification methodologies (OVM/UVM).
Strong understanding of ASIC design flow and verification techniques.
Excellent problem-solving and debugging skills.
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- Experience with formal verification tools and methodologies.
- Familiarity with scripting languages (e.g., Python, Perl) for automation tasks.
- Knowledge of industry-standard protocols and interfaces (e.g., PCIe, AXI, AHB).
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- Opportunities for professional growth and career advancement.
- Vibrant and inclusive work culture that values collaboration and innovation.
If you're ready to take your career to the next level and contribute to groundbreaking projects, we want to hear from you!
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Skills: design,verilog,rtl design,communication,universal verification methodology (uvm)
