Design Engineer

Title: PCIe-CXL-Micro-Architect

Location: Bangalore

Salary: Compensation is based on expertise and experience.

Level of Experience: Senior

Work Arrangement: Onsite

1. Senior RTL Design Engineer with experience in

Architecting/designing/integrating PCIe Root Complex, Host Bridge, Root

Port, Address Translation Service and IOMMU for Server side PCIe Root

Complex functionality. Ability to use IPs from standard vendors and

Architect/Design any additional logic modules to be able to integrate with

rest of the ASIC modules in the Server SoC ASICs. A thorough

understanding of System level functionality and how PCIe/CXL Root

Complex modules integrate with Cache-Coherent NoCs, Memory

Subsystems, CPU complexes through AMBA bus protocols is required.

Also, need to design and integrate CXL.io and CXL.mem functionality into

the Root Complex and Root Port Modules by configuring the IPs from

Standard Vendors like Synopsys.

2. Work with our design and verification teams spread across Armenia, India,

China, and the backend/PR team located in China.