2+ years of experience in the field of front-end design, synthesis and STA
In-depth knowledge of synthesis, static timing analysis and constraints development
In-depth knowledge of RTL design fundamentals
In-depth knowledge of Verilog and System-Verilog
In-depth knowledge of front-end tools (Verilog compilers/simulators, linters, clock-domain crossing checkers, RTL synthesis, STA)
DFT knowledge is a plus
Good knowledge of scripting languages such as Perl, Tcl and Python
Strong communication and presentation skills
