WHAT YOU DO AT AMD CHANGES EVERYTHING
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LOCATION: Bangalore
About The Department
The Physical Design team of the GPU Technologies and Engineering Group is responsible for the physical layout of next generation GPU SoCs in the most advanced fabrication nodes. The team collaborates with IP teams and other AMD functions across the globe to assemble the SoC design and ensure that it will be sent for fabrication at spec and on schedule. The designs are executed hierarchically to accommodate the large design sizes and provide reasonable turn-around time in all stages of the design flow.
The Role
The Physical Design Team Is Responsible For Following Tasks
- Floorplanning - Chip sizing; block sizing; IP placement; pad placement
- Synthesis - Synthesizing RTL inputs to generate gate level netlist
- Power Distribution - Create power grid for digital logic; analog power routing
- Clock Distribution - Clock trees and clock mesh for all clocks
- Block Place & Route - Gate level netlist to fully routed layout using industry standard tools
- Chip Place & Route - Gate level netlist to fully routed layout using industry standard tools
- Timing Closure - Static Timing Analysis of all clock domains
- EM/IR Analysis - Verification of power distribution for electro-migration and IR performance
- Physical Verification - Ensure that all design rules are met for correct and high-yield fabrication; LVS
- Tape-out - Shipment to foundry for fabrication
What You'll Be Doing
- To effectively work within a team of other Physical Design Engineers and be responsible for the Physical Design for a portion of one of our ASIC's.
- Tasks to include Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off.
- PD Flow development and scripting.
- Technical problem solving.
What You'll Learn
- Floorplanning - Chip sizing; block sizing; IP placement; pad placement
- Power Distribution - Create power grid for digital logic; analog power routing
- Clock Distribution - Clock trees and clock mesh for all clocks
- Block Place & Route - Gate level netlist to fully routed layout using industry standard tools
- Chip Place & Route - Gate level netlist to fully routed layout using industry standard tools
- Timing Closure - Static Timing Analysis of all clock domains
- EM/IR Analysis - Verification of power distribution for electro-migration and IR performance
- Physical Verification - Ensure that all design rules are met for correct and high-yield fabrication; LVS
- Tape-out - Shipment to foundry for fabrication
Key Qualifications
- 3rd Year student pursuing a bachelor's degree in Electronics or Computer Engineering
- Returning to school following the co-op term
- Written and verbal communication and presentation skills
Preferred Qualifications
- Strong semi-conductor device physics knowledge.
- Transistor and/or logic circuit design knowledge.
- Programming experience (C++/C/Perl/Python/Verilog/UNIX scripting).
- Excellent analytical and problem-solving skills along with attention to details.
- Strong communication, Time Management, and Presentation Skills.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process. 
