BT Design Verification Sr Lead Engineer

• QCTs Bangalore Wireless R&D Bluetooth HW team is looking for experienced Wireless HW Design Verification engineers to work on Qualcomm s best in class chipsets for mobile phones, wearables and IOT
• Candidate will be working with ASIC designs on the latest technology nodes and on cutting edge next-generation Wireless PAN technologies (Bluetooth, UWB, Thread, Zigbee etc)
• This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, emulation, GLS and Formal techniques
• The role also requires deep understanding of the Bluetooth Hardware Architecture
• Candidate will require close interactions with Global Design, Systems, SoC, Validation and FW teams for design convergence and required to work with minimal supervision
• Candidate must be able to take ownership of IP/Block/Sub-System verification
• Incumbent will be analyzing HW design spec and develop a verification test plan/strategy for it, breaking down the work for new features, perform feasibility studies, estimate effort, and mitigate risk
• The role also required the candidate to mentor new joiners and less experienced colleagues
• The candidate will work with design team on RTL debug during Pre-silicon HW development phase

Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

• 6-10 years of strong experience in design verification
• Strong knowledge of HDLs like Verilog, System Verilog
• Proven experience of writing efficient constraint random tests
• Proven experience of building or maintaining a medium to complex SV/UVM environments
• Strong debugging and analytical skills and independent problem-solving ability
• Proficient in debugging RTL/TB issues using Verdi or similar tools
• Demonstrate good judgment in selecting methods and techniques for obtaining solutions
• Strong communication skills, both written and verbal, with ability to evaluate and create testplans detailing complex features and relationships
• bachelors or masters Degree in Engineering in Electronics, VLSI, Communications or related field

Minimum Qualifications:

• bachelors Degree in Engineering in Electronics, VLSI, Communications or related field
• 6 years of VLSI industry experience in verification

Preferred Qualifications:

• Exposure to Bluetooth/BLE/UWB Technologies
• Knowledge on scripting languages such as Perl and(or) Python

Skills:

• Functional Verification, Functional/Code Coverage, SystemVerilog Assertions, Universal Verification Methodology (UVM), Verification IP (VIP) Integration, SoC Integration, Formal Verification