ASIC RTL Design Engineer

Dear Candidate

We, Cyient is hiring for ASIC RTL Design Engineer (Offshore-Onshore Model based Global Product Solution) Position.

Base Location: Bangalore

Experience Range: 3-5 Years

Job Description:

• Good understanding of Verilog and design concepts
• Hands on experience in RTL coding and verification
• Good debugging skills
• Scripting experience is a plus
• Hands on experience in synthesis
• Should have good understanding on constraints and techniques to improve design performance
• Any knowledge or hands-on in STA is a bonus

Best Regards

Rajani Kant Sharma

Sr Recruiter: Global Lateral Hiring: Semicon Vertical

Cyient