ASIC Digital Design Staff Engineer

Requirements:

- BS/BE/Masters in EE with 5+ years of relevant experience in the verification of IP cores and/or SOC verification.

- Experience in developing HVL based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage.

- HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and relevant debugging tools.

- Exposure to verification methodologies such as UVM/VMM/OVM is required.

- Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired.

- Exposure to IP design and verification processes including VIP development is an added advantage.

- Basic understanding of functional & Code coverage.

- It is essential that the individual has good written and oral communication skills and is able to demonstrate good analysis, debug and problem-solving skills and be self-driven.

Our Silicon IP business is all about integrating more capabilities into an SoCfaster. We offer the world's broadest portfolio of silicon IPpredesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.